1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H
37 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALEN. */
39 #include <rdma/ib_user_ioctl_verbs.h>
42 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
51 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
55 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
58 /* Increment this value if any changes that break userspace ABI
59 * compatibility are made.
61 #define MLX5_IB_UVERBS_ABI_VERSION 1
63 /* Make sure that all structs defined in this file remain laid out so
64 * that they pack the same way on 32-bit and 64-bit architectures (to
65 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
66 * In particular do not use pointer types -- pass pointers in __u64
70 struct mlx5_ib_alloc_ucontext_req {
71 __u32 total_num_bfregs;
72 __u32 num_low_latency_bfregs;
76 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
79 enum mlx5_ib_alloc_uctx_v2_flags {
80 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
82 struct mlx5_ib_alloc_ucontext_req_v2 {
83 __u32 total_num_bfregs;
84 __u32 num_low_latency_bfregs;
91 __aligned_u64 lib_caps;
94 enum mlx5_ib_alloc_ucontext_resp_mask {
95 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
96 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
99 enum mlx5_user_cmds_supp_uhw {
100 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
101 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
104 /* The eth_min_inline response value is set to off-by-one vs the FW
105 * returned value to allow user-space to deal with older kernels.
107 enum mlx5_user_inline_mode {
108 MLX5_USER_INLINE_MODE_NA,
109 MLX5_USER_INLINE_MODE_NONE,
110 MLX5_USER_INLINE_MODE_L2,
111 MLX5_USER_INLINE_MODE_IP,
112 MLX5_USER_INLINE_MODE_TCP_UDP,
116 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
117 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
118 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
119 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
120 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
123 struct mlx5_ib_alloc_ucontext_resp {
127 __u32 cache_line_size;
128 __u16 max_sq_desc_sz;
129 __u16 max_rq_desc_sz;
130 __u32 max_send_wqebb;
132 __u32 max_srq_recv_wr;
134 __u16 flow_action_flags;
136 __u32 response_length;
140 __u8 clock_info_versions;
141 __aligned_u64 hca_core_clock_offset;
143 __u32 num_uars_per_page;
144 __u32 num_dyn_bfregs;
145 __u32 dump_fill_mkey;
148 struct mlx5_ib_alloc_pd_resp {
152 struct mlx5_ib_tso_caps {
153 __u32 max_tso; /* Maximum tso payload size in bytes */
155 /* Corresponding bit will be set if qp type from
156 * 'enum ib_qp_type' is supported, e.g.
157 * supported_qpts |= 1 << IB_QPT_UD
159 __u32 supported_qpts;
162 struct mlx5_ib_rss_caps {
163 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
164 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
168 enum mlx5_ib_cqe_comp_res_format {
169 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
170 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
171 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
174 struct mlx5_ib_cqe_comp_caps {
176 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
179 enum mlx5_ib_packet_pacing_cap_flags {
180 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
183 struct mlx5_packet_pacing_caps {
184 __u32 qp_rate_limit_min;
185 __u32 qp_rate_limit_max; /* In kpbs */
187 /* Corresponding bit will be set if qp type from
188 * 'enum ib_qp_type' is supported, e.g.
189 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
191 __u32 supported_qpts;
192 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
196 enum mlx5_ib_mpw_caps {
197 MPW_RESERVED = 1 << 0,
198 MLX5_IB_ALLOW_MPW = 1 << 1,
199 MLX5_IB_SUPPORT_EMPW = 1 << 2,
202 enum mlx5_ib_sw_parsing_offloads {
203 MLX5_IB_SW_PARSING = 1 << 0,
204 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
205 MLX5_IB_SW_PARSING_LSO = 1 << 2,
208 struct mlx5_ib_sw_parsing_caps {
209 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
211 /* Corresponding bit will be set if qp type from
212 * 'enum ib_qp_type' is supported, e.g.
213 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
215 __u32 supported_qpts;
218 struct mlx5_ib_striding_rq_caps {
219 __u32 min_single_stride_log_num_of_bytes;
220 __u32 max_single_stride_log_num_of_bytes;
221 __u32 min_single_wqe_log_num_of_strides;
222 __u32 max_single_wqe_log_num_of_strides;
224 /* Corresponding bit will be set if qp type from
225 * 'enum ib_qp_type' is supported, e.g.
226 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
228 __u32 supported_qpts;
232 enum mlx5_ib_query_dev_resp_flags {
233 /* Support 128B CQE compression */
234 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
235 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
238 enum mlx5_ib_tunnel_offloads {
239 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
240 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
241 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
242 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
243 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
246 struct mlx5_ib_query_device_resp {
248 __u32 response_length;
249 struct mlx5_ib_tso_caps tso_caps;
250 struct mlx5_ib_rss_caps rss_caps;
251 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
252 struct mlx5_packet_pacing_caps packet_pacing_caps;
253 __u32 mlx5_ib_support_multi_pkt_send_wqes;
254 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
255 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
256 struct mlx5_ib_striding_rq_caps striding_rq_caps;
257 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
261 enum mlx5_ib_create_cq_flags {
262 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
265 struct mlx5_ib_create_cq {
266 __aligned_u64 buf_addr;
267 __aligned_u64 db_addr;
270 __u8 cqe_comp_res_format;
274 struct mlx5_ib_create_cq_resp {
279 struct mlx5_ib_resize_cq {
280 __aligned_u64 buf_addr;
286 struct mlx5_ib_create_srq {
287 __aligned_u64 buf_addr;
288 __aligned_u64 db_addr;
290 __u32 reserved0; /* explicit padding (optional on i386) */
295 struct mlx5_ib_create_srq_resp {
300 struct mlx5_ib_create_qp {
301 __aligned_u64 buf_addr;
302 __aligned_u64 db_addr;
310 __aligned_u64 sq_buf_addr;
311 __aligned_u64 access_key;
315 /* RX Hash function flags */
316 enum mlx5_rx_hash_function_flags {
317 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
321 * RX Hash flags, these flags allows to set which incoming packet's field should
322 * participates in RX Hash. Each flag represent certain packet's field,
323 * when the flag is set the field that is represented by the flag will
324 * participate in RX Hash calculation.
325 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
326 * and *TCP and *UDP flags can't be enabled together on the same QP.
328 enum mlx5_rx_hash_fields {
329 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
330 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
331 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
332 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
333 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
334 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
335 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
336 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
337 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
338 /* Save bits for future fields */
339 MLX5_RX_HASH_INNER = (1UL << 31),
342 struct mlx5_ib_create_qp_rss {
343 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
344 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
345 __u8 rx_key_len; /* valid only for Toeplitz */
347 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
352 struct mlx5_ib_create_qp_resp {
357 struct mlx5_ib_alloc_mw {
364 enum mlx5_ib_create_wq_mask {
365 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
368 struct mlx5_ib_create_wq {
369 __aligned_u64 buf_addr;
370 __aligned_u64 db_addr;
376 __u32 single_stride_log_num_of_bytes;
377 __u32 single_wqe_log_num_of_strides;
378 __u32 two_byte_shift_en;
381 struct mlx5_ib_create_ah_resp {
382 __u32 response_length;
387 struct mlx5_ib_burst_info {
389 __u16 typical_pkt_sz;
393 struct mlx5_ib_modify_qp {
395 struct mlx5_ib_burst_info burst_info;
399 struct mlx5_ib_modify_qp_resp {
400 __u32 response_length;
404 struct mlx5_ib_create_wq_resp {
405 __u32 response_length;
409 struct mlx5_ib_create_rwq_ind_tbl_resp {
410 __u32 response_length;
414 struct mlx5_ib_modify_wq {
419 struct mlx5_ib_clock_info {
423 __aligned_u64 cycles;
428 __aligned_u64 overflow_period;
431 enum mlx5_ib_mmap_cmd {
432 MLX5_IB_MMAP_REGULAR_PAGE = 0,
433 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
434 MLX5_IB_MMAP_WC_PAGE = 2,
435 MLX5_IB_MMAP_NC_PAGE = 3,
436 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
437 MLX5_IB_MMAP_CORE_CLOCK = 5,
438 MLX5_IB_MMAP_ALLOC_WC = 6,
439 MLX5_IB_MMAP_CLOCK_INFO = 7,
440 MLX5_IB_MMAP_DEVICE_MEM = 8,
444 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
447 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
449 MLX5_IB_CLOCK_INFO_V1 = 0,
452 struct mlx5_ib_flow_counters_desc {
457 struct mlx5_ib_flow_counters_data {
458 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
463 struct mlx5_ib_create_flow {
464 __u32 ncounters_data;
467 * Following are counters data based on ncounters_data, each
468 * entry in the data[] should match a corresponding counter object
469 * that was pointed by a counters spec upon the flow creation
471 struct mlx5_ib_flow_counters_data data[];
474 #endif /* MLX5_ABI_USER_H */